1. Technical Field
This disclosure relates to receiver circuits, and more particularly, to a receiver circuit immune to noise superimposed to a signal during or shortly after a transition.
2. Description of the Related Art
Digital circuits may be subject to noisy signals. Noisy signals may result in bit errors when converting the analog waveforms to digital signals. Noise suppression can reduce noise. For example, in receiver circuits that convert (noisy) analog input signals to digital on-chip signals, hysteresis is one means to suppress noise. Instances of slope reversal caused by reflections on ill terminated signal traces and extremely slow transitions (e.g., in burn-in test setups for semiconductor device tests) superimposed with random noise can cause incomplete pulses and spikes of the on-chip digital signals. This can cause malfunction of circuitry that assumes certain minimum and maximum pulse widths.
A structure of a differential amplifier-based receiver is shown in FIG. 1. A first stage 10 includes an N-channel differential pair 11 with a P-channel current mirror 13. A second stage 12 is realized by an inverter 14. One advantage of this configuration is that a switch-point is very well defined by the reference voltage VREF. The switch-point is the input voltage level (VIN) at which the output switches. For good system performance, a hysteresis of about 5-10% of the input voltage (VIN) swing is desirable. For stub series terminated logic (SSTL-2, for example), this would be a few tens of mV""s.
The prior art realization of receivers with hysteresis does not typically provide sufficient hysteresis control. The prior art provides weak controllability (i.e., achieving a small shift of the switch point based on the output state) or slow reaction time (i.e., incapability to suppress fast noise spikes). Negative noise pulses typically occur shortly after a transition (change in state). Such noise (or slope reversal noise) is typical for ill matched or unterminated clock traces as a consequence of reflections.
In U.S. Pat. No. 5,796,281, adding additional current to an output node of a first stage (differential amplifier) creates hysteresis. Note however, that the amount of current added is not well controlled and thus the amount of hysteresis is not well controlled. To achieve small hysteresis the transistors (for example, Q2 in U.S. Pat. No. 5,796,281) that switch the additional current have to be a small fraction of the size of main transistors of the amplifiers in U.S. Pat. No. 5,796,281. For speed purposes, however, these transistors are close to their minimum size already. Thus, it is very difficult, if not impossible, to achieve small and controlled amounts of hysteresis. Note that a hysteresis, which is too large, will also adversely affect speed. FIGS. 26.4 and 26.5 of Baker et al., xe2x80x9cCMOS Circuit Design, Layout and Simulation,xe2x80x9d IEEE press 1998, also show circuitry for providing additional current at an output node of a first stage to attempt to control hysteresis. This circuit suffers from the same drawbacks as described above.
In other attempts to introduce controlled small amounts of hysteresis, a reference voltage is shifted based on the output state of the receiver. Although some controllability is achieved, the switching process takes too long to effectively help suppress noise spikes. It also requires two reference voltage generators, which cause additional current consumption. See e.g., U.S. Pat. No. 4,775,807.
In U.S. Pat. No. 4,745,365, the solution described consumes even more power by utilizing two receivers with offset VREF. Both receivers have to run at the same speed.
Even with the limited control of hysteresis, the receiver systems of the prior art may also suffer from the drawback of oscillations in the case of extremely slow transitions or static input signals with a value between the switch points (state transition changes) of the receiver circuit. This makes these approaches unfeasible where there is no strict lower limit on the slew rate.
Therefore, a need exists for a receiver design which has the same power and receiving delay as the conventional (e.g., differential amplifier and inverter stage of FIG. 1) receiver, but also is highly immune to negative noise pulses occurring shortly after a transition.
A receiver circuit provides a first stage having an input for receiving input signals and an output node. The first stage includes an amplifier. A second stage has an input coupled to the output of the first stage. The second stage includes a switching circuit coupled to the output node of the first stage for driving the input signals by favoring a rising edge or a falling edge in accordance with a control signal. The second stage also includes a feedback loop coupled to an output of the second stage. The feedback loop provides the control signal for switching the switching circuit to favor the rising edge or falling edge.
Another receiver circuit includes a first circuit having two modes of operation controlled by a feedback loop. The feedback loop is connected to an output of the first circuit, and the modes of operation include a first mode having a quicker response to an input falling signal edge than a second mode and a second mode with a quicker response to an input rising signal edge than the first mode. A driver stage is integrated into the first circuit to favor the rising edge or the falling edge in accordance with a control signal provided by the feedback loop.
In other embodiments, the second stage may include an inverter coupled to the output of the first stage, and the inverter preferably has an output representing the output of the receiver circuit. The second stage may include a first transistor coupled between the output of the inverter and a supply voltage and a second transistor coupled between the output of the inverter and a ground, wherein the first and second transistors have different strengths relative to transistors of the inverter to provide skewed driver strength for driving the input signals to the output of the second stage.
In still other embodiments, the second stage may include current sources coupled to an input of the inverter and coupled to gates of the first and second transistors through the switching circuit to provide driving current to the inverter and the first and second transistors in accordance with the control signal. The switching circuit may include switching elements switched by the control signal to alternately select circuit elements, which favor a rising edge and a falling edge. The switching elements may include CMOS transfer gates. The amplifier may include a differential amplifier and/or a transconductance amplifier. The input signals may include analog signals and the receiver circuit preferably suppresses noise of the analog signals. The output preferably represents a digital logic state. The feedback loop may include delay elements such that noise after a transition in the input signals is suppressed for a delay period provided by the delay elements provided by the delay elements. The feedback loop may be programmable to adjust the delay period provided by the delay elements. The feedback loop may be controlled by a control circuit to adjust the delay period provided by the delay elements. The delay period may be controlled in accordance with an input signal input to the receiver circuit. A delay value of the delay elements is preferably less than half a clock period of the input signal.
Another receiver circuit, in accordance with the present invention, includes a first stage having an input for receiving input signals and an output node, the first stage including an amplifier, and a second stage having an input coupled to the output of the first stage. The second stage includes an inverter coupled to the output of the first stage, the inverter having an output representing the output of the receiver circuit and including transistors, a first transistor coupled between the output of the inverter and a supply voltage, and a second transistor coupled between the output of the inverter and a ground, wherein the first and second transistors have different strengths relative to the transistors of the inverter to favor a transition edge being driven to suppress noise after the transition edge. A feedback loop is coupled from the output of the inverter for enabling switching elements, the switching elements being switched in accordance with the output of the inverter to favor the transition edge being driven at the output of the inverter.
In other embodiments, the first transistor may include a P-channel transistor and the inverter may include an N-channel transistor and a relative strength ratio between the P-channel transistor and the N-channel transistor is preferably between about 3:1 to about 10:1. The second transistor may include an N-channel transistor and the inverter may include an P-channel transistor and a relative strength ratio between the N-channel transistor and the P-channel transistor is preferably between about 3:1 to about 10:1. Current sources may be coupled to an input of the inverter and coupled to gates of the first and second transistors through the switching elements to provide driving current to the inverter and the first and second transistors in accordance with a control signal on the feedback loop.
In still other embodiments, the switching elements may include CMOS transfer gates. The amplifier may include a differential amplifier and/or a transconductance amplifier. The input signals may include analog signals and the receiver circuit preferably suppresses noise of the analog signals. The inverter output preferably represents a digital logic state. The feedback loop may include delay elements such that noise after a transition in the input signals is suppressed for a delay period provided by the delay elements provided by the delay elements. A delay value of the delay elements is preferably less than half a clock period of the input signal.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.